Impact des TSVs (Through Silicon Vias) sur les circuits CMOS nanom´etriques – Etude et conception d’un détecteur ´ verticalement int´egr´e de rayon X.

Abstract

Current innovations in electronics combine performance, size and cost criteria. Nevertheless, in the all-digital era, the 2D technology and the fabrication of CMOS Integrated Circuits are approaching their ultimate limits. As a result, the use of 3D technology in the fabrication of different Integrated Circuits is becoming very appealing. Among the aspects of the 3D Integration we find the Through Silicon Vias (TSVs), short vertical interconnects that convey the different layers all kind of signals. 3D integration, first introduced for memory chips, has later found increasing application to other domains in microelectronics, particularly in radiation detectors. These imaging instrumentations are being used recently in many fields such as for the next generation free electron lasers (FELs) that are currently being developed in a few research centers worldwide. Among these, the X-ray Free Electron Lasers (XFELs). To fully exploit the potential of XFEL facilities, a new generation of image sensors using vertical integration technologies, as Through Silicon Vias (TSVs), and an enhanced characteristic with respect to currently-available devices has to be manufactured. Therefore, this PhD work consists on the investigation of the impact of TSVs interconnects on CMOS circuits as well as the study and design of a vertically integrated X-ray detector. To this purpose, a numerical and an analytical analysis of CMOS circuits with a 3D-TSV technology is investigated. The most relevant technological parameters regarding TSVs are optimized. The knowledge gained from this analysis is used in the development for the multilayer large area X-ray imaging detector within the framework of an R&D project PixFEL. These imaging instrumentations are studied and optimized first by means of TCAD simulations, considering the most relevant geometry and process parameters, allowing for structures with minimum edge size and larger operating bias conditions. The layout of wafers including different structures of edgeless sensors, arrays, and test structures are designed. The fabricated devices are electrically characterized, and the feasibility of the process is demonstrated along this work of this thesis.