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dc.contributor.authorسليماني, أيوب
dc.contributor.authorبن سلامة, عاشور
dc.date.accessioned2017-11-20T14:05:43Z
dc.date.available2017-11-20T14:05:43Z
dc.date.issued2017-10-26
dc.identifier.urihttp://hdl.handle.net/123456789/136187
dc.description.abstractReversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This thesis presents a complete design of a new (reversible/quantum) arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented QALU can produce the largest number of arithmetic and logic functions (28) and have the smallest number of quantum cost and delay compared with existing designsfr_FR
dc.language.isoarfr_FR
dc.publisherجامعة الإخوة منتوري قسنطينةfr_FR
dc.subjectLogique reversiblefr_FR
dc.subjectporte quantiquefr_FR
dc.subjectcircuit quantiquefr_FR
dc.subjectadditionneur completfr_FR
dc.subjectfonctions arithmétiques et logiquesfr_FR
dc.subjectunité de logique arithmétiquefr_FR
dc.subjectunité centrale de traitementfr_FR
dc.subjectReversible Logicfr_FR
dc.subjectquantum gatefr_FR
dc.subjectquantum circuitfr_FR
dc.subjectfull adderfr_FR
dc.subjectarithmetic and logic functionsfr_FR
dc.subjectarithmetic logic unitfr_FR
dc.subjectcentral processing unitfr_FR
dc.subjectالمنطق العكوسfr_FR
dc.subjectالبوابة الكوانتيةfr_FR
dc.subjectالدارة الكوانتيةfr_FR
dc.subjectالجامع الكاملfr_FR
dc.subjectالعمليات المنطقية والحسابيةfr_FR
dc.subjectوحدة الحساب والمنطقfr_FR
dc.subjectوحدة المعالجة المركزيةfr_FR
dc.titleالحوسبة الكوانتية و تطبيقاتهاfr_FR
dc.typeThesisfr_FR


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